With the ever increasing microminiaturization of semi-conductor integrated circuits, and, thus, increasing lateral semiconductor device densities in the integrated circuit, in recent years a major portion of the integrated circuit art has been moving in the direction of utilizing lateral dielectric isolation in order to laterally electrically isolate the densely packed devices from each other.
One approach for forming lateral dielectric isolation which has been increasingly utilized in the art involves the formation of recessed silicon dioxide lateral isolation regions, usually in the epitaxial layer where the semiconductor devices are to be formed, through the expedient of first selectively etching a pattern of recesses in the layer of silicon, and then thermally oxidizing the silicon in the recesses with appropriate oxidation blocking masks, e.g., silicon nitride masks, to form recessed or inset regions of silicon dioxide which provide the lateral electrical isolation. Representative of the prior art teaching in this area are U.S. Pat. No. 3,648,125 and an article entitled, "Locos Devices", E. Kooi et al, Philips Research Report 26, pp. 166 - 180 (1971). While this approach has provided good lateral electrical isolation, it had its limitations. The etched recesses generally were widest at the surface and tended to taper more narrowly, with increasing depth from the surface. Thus, such dielectric isolation had its limits with respect to depth, i.e, the deeper the isolation was to extend, the wider the recess had to be, thereby consuming the valuable lateral "real estate". As a result, relatively deep recessed silicon dioxide structures would tend to offset the very reason for selecting dielectric isolation over lateral junction isolation, that of narrower lateral device dimensions and, consequently, greater lateral device densities.
One major prior art expedient for limiting the depth to which recessed silicon dioxide lateral isolation need to be formed involves the combination of recessed silicon dioxide at the surface of the silicon layer with a junction isolation, e.g., p-type isolation region, below the recessed oxide. Such hybrid structures are described in the prior art, for example, in U.S. Pat. No. 3,858,231 or in the previously mentioned article from the Philips Research Report. The P+ isolation region beneath the recessed oxide may be formed either by out-diffusion from a buried P+ region in the silicon substrate below the silicon epitaxial layer or by a P+ diffusion into the etched recess prior to the thermal oxidation to form the silicon dioxide inset.
FIG. 1 of the drawings shows a typical prior art structure of this type. N- epitaxial region 10 is formed on P- substrate 11. The device regions 12 in the substrate are electrically isolated by enclosures comprising silicon dioxide regions 13 and P+ isolation regions 14. The devices consist of emitter 15, base 16, buried subcollector 17, respective metal contacts 18, 19 and 20 to each, and passivation layer 21.
Recently, the art of etching recesses in silicon has developed processes for etching substantially vertical-walled recesses in silicon. Typical of these new etching techniques is described in the article entitled, "The Etching Of Deep Vertical-Walled Patterns In Silicon", A. I. Stoller, R.C.A. Review, June 1970, pp. 271 - 275. With such new vertical-walled etching techniques, it has now become possible to substantially narrow the lateral dimensions of recessed silicon dioxide regions. However, with the narrowing of the lateral dimensions of such recessed silicon dioxide regions, further problems have been presented to the art, particularly where such recessed silicon dioxide regions have been used to provide isolation to bipolar integrated circuits.
With reference to FIG. 2, one potential problem encountered by the utilization of deep vertical-walled recessed oxide extending through the epitaxial layer will be illustrated. The interface between P- substrate 22 and epitaxial layer 23 is phantom line 24. Thus, recessed silicon dioxide regions 25 extend beyond the interface into the substrate 22. However, because of the narrowed lateral dimensions in each transistor device, buried subcollector 26 must abut the lower portions of substantially vertical-walled silicon regions 25. This is necessary because emitter region 27 abuts the vertical-walled silicon dioxide region 25, and the buried subcollector region 26 must be disposed below all portions of the emitter 27 in order for the transistor to function properly. Since the buried subcollector is driven both vertically and laterally into the substrate during the high temperature thermal oxidation necessary to produce recessed silicon dioxide regions 25, as well as during all subsequent high heat diffusion and oxidation cycles in the transistor formation, there is a strong tendency for adjacent subcollector regions such as regions 26 and 26' to laterally diffuse and meet each other beneath recessed silicon dioxide regions 25 as shown at point 28 of the drawing.
This problem is difficult to avoid since in the formation of the integrated circuit the buried subcollector 26 must initially be placed sufficiently close to that portion of the substrate to which the recessed silicon dioxide region 25 is to extend. Otherwise, there is a distinct danger that the buried subcollector will not extend beneath those portions of emitter 27 which abut recessed silicon dioxide region 25. It should be noted that even where the buried subcollector 26 is a relatively shallow region and an attempt is made to drive recessed silicon dioxide region 25 as deep into substrate 22 as possible, the problem of adjacent buried subcollectors shorting into each other is still pronounced since even as the recessed oxide region 25 is driven deep into the substrate, the N-type impurities from subcollector region 26 will be driven down ahead of silicon dioxide region 25 in a "snow-plough" as described in the above mentioned Philips Research Report article, particularly at page 167. This is especially the case with the P- substrate and an N+ buried subcollector because of the tendency of inversion to readily occur in P- substrates.
In addition, as will be illustrated with respect to FIG. 3, even where the vertical-walled recessed silicon dioxide regions 30 are used in a hybrid structure similar to that of FIG. 1 in combination with buried P+ isolation regions 31, the narrowed device lateral dimensions present a similar problem. Again, since buried subcollector 32 must extend below all of emitter region 33 which abuts the recessed silicon dioxide region 30, there is a resulting P+/N+ junction 33 which, of course, causes the breakdown voltages of the PN-junction isolation to be undesirably low.